Recently, operating clock frequencies have been increased in integrated circuit devices such as microcomputers. For this reason, the following constitution is frequently adopted: a clock multiplication circuit constructed using a PLL (i.e., Phase Locked Loop) circuit is incorporated in an integrated circuit device; and externally supplied clock signals are internally multiplied, and supplied to CPU and the like. Some of such clock multiplication circuits are so constructed that multiplied clock signals are generated and outputted by digital PLL (i.e., DPLL) operation using a ring oscillator.
Ring oscillators are constructed by annularly connecting a plurality of delay gates (e.g. NOT gates), and generate high-speed clock signal by digital oscillating operation. However, in the NOT gates and the like, the gate delay time is varied according to supply voltage. When the supply voltage fluctuates, the frequency of multiplied clock signals outputted from a multiplication circuit also fluctuates. This is a jitter effect.
For this reason, when a multiplication circuit of the above-mentioned constitution is used, the following measures are taken: an internal power supply generation circuit constructed of a series regulator and the like is incorporated in an integrated circuit device. Thus, even when supply voltage externally supplied fluctuates, stable voltage can be supplied to a clock multiplication circuit, other internal circuits, and the like.
There are various technologies for stabilizing the oscillating operation of a clock multiplication circuit. For example, Japanese Unexamined Patent Publication No. 2000-165234 discloses a PLL circuit. This PLL circuit is so constructed that it comprises: a first PLL module that uses as operating power supply internal voltage generated by an internal power supply generation circuit, and generates intermediate clock signals based on an externally supplied reference clock signal; and a second PLL module that uses external power supply as operating power supply, and generates internal clock signals based on the above-mentioned intermediate clock signals.
Japanese Unexamined Patent Publication No. 2002-111484 discloses another technology. In this technology, a PLL circuit is so constructed that it comprises: a phase comparator; a first circuit that forms a signal of a level corresponding to the output signal of the phase comparator; and a second circuit that generates a clock signal of a frequency corresponding to the output level of the first circuit. A low-pass filter is placed between the power supply terminal of the first circuit and the power supply terminal of the second circuit. Thus, noise produced in the second circuit is prevented from being transmitted to the first circuit through a power line, and reduction of jitter effect is accomplished in the PLL circuit.
In the internal circuit of an integrated circuit such as a digital circuit that operates with supply of a multiplied clock signal, the following occurs: the consumption current varies according to the state of operation of a circuit portion that operates in synchronization with clock. Therefore, when internal power supply stabilized by an internal power supply generation circuit is supplied both to a multiplication circuit and to the internal circuit, a problem arises. The internal supply voltage fluctuates depending on the operating state on the internal circuit side. However, the technologies according to the prior arts do not give consideration to this problem at all, and with these technologies, occurrences of jitter effect due to fluctuation in internal supply voltage cannot be avoided.
Further, for example, single-chip microcomputers are mounted with clock signal output circuits for generating and supplying system clock signals. Some of the clock signal output circuits are provided with a function of multiplying the frequency of a clock signal to cope with increase in the operating clock frequency of microcomputers. When a clock signal of a constant frequency is continuously outputted, sharp noise peaks are produced in its fundamental frequency and harmonic content. When CPU or a peripheral circuit operates in synchronization with the clock signal, power consumption more greatly fluctuates, and the noise level is further raised.
One of technologies for solving the above problem is disclosed in Japanese Unexamined Patent Publication No. 2001-148690, which corresponds to U.S. Pat. No. 6,407,606. As illustrated in FIG. 16, this technology is such that: a clock forming unit 101 so constructed that it comprises a ring oscillator is used to generate clock signals in m-phases whose frequencies are identical and whose phases are shifted by a certain amount. The clock signals are supplied to a selection processing unit 102. A dithering control unit 103 supplies the selection processing unit 102 with a control signal and causes the unit 102 to select one from among clock signals in m-phases in sequence. The dithering control unit 103 causes the selection processing unit 102 to output it from an output terminal 104. Thus, the phase of the clock signals is caused to disperse the peaks in frequency spectrum with respect to noise.
However, there is a problem in realizing the constitution disclosed in Japanese Unexamined Patent Publication No. 2001-148690. In addition to the clock forming unit 101 that generates clock signals in m phases, the dithering control unit 103 and the selection processing unit 102 must be provided. Therefore, an additional circuit area is required on the chip of the microcomputer.